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[VHDL-FPGA-Verilog] count

Description: 自己编制的计数器的verilog代码 希望能对大家有所帮助-Prepared their own counter Verilog code for all of us hope to be helpful
Platform: | Size: 1024 | Author: 舒畅 | Hits:

[VHDL-FPGA-Verilog] counterfour

Description: verilog code for counter four
Platform: | Size: 1024 | Author: vmreddy | Hits:

[VHDL-FPGA-Verilog] Counter_Design_Block

Description: Here is a code for a simple counter based on verilog
Platform: | Size: 11264 | Author: spectrojin | Hits:

[VHDL-FPGA-Verilog] S5

Description: VERILOG SOURCE CODE FOR N MODULO COUNTER
Platform: | Size: 6144 | Author: SUNIL | Hits:

[VHDL-FPGA-Verilog] mod10asynchro

Description: this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
Platform: | Size: 23552 | Author: swapna | Hits:

[VHDL-FPGA-Verilog] mod6asynchro

Description: this is a code for mod-6 asynchronous counter in verilog.
Platform: | Size: 24576 | Author: swapna | Hits:

[VHDL-FPGA-Verilog] asynchro2bitupdownneg

Description: this a verilog code for asynchronous 2 bit up down counter with negative edge triggered.-this is a verilog code for asynchronous 2 bit up down counter with negative edge triggered.
Platform: | Size: 27648 | Author: swapna | Hits:

[VHDL-FPGA-Verilog] VerilogCode_BCD_counter

Description: Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
Platform: | Size: 1024 | Author: Rahul | Hits:

[VHDL-FPGA-Verilog] Counter.v

Description: Custom verilog code for up counter with Interrupt.
Platform: | Size: 1024 | Author: Moganeshwaran | Hits:

[VHDL-FPGA-Verilog] johnsonverilog

Description: 本verilog代码实现了johnson计数器，也就是控制流水灯的程序，具体为从左到右和从右到左以及停止的流水灯操作-The verilog code of the johnson counter, that is, water lamp control procedures, specifically for the left to right and from right to left and stop the flow lamp operation
Platform: | Size: 318464 | Author: 张扬 | Hits:

[VHDL-FPGA-Verilog] verilog.tar

Description: counter.v...its verilog code for counter
Platform: | Size: 1024 | Author: vinay | Hits:

[VHDL-FPGA-Verilog] Counter

Description: 用VERILOG语言实现的74*163 计数器，代码十分简单易懂，适合数字逻辑电路实验的初学者-With the VERILOG language implementation of the 74* 163 counter, the code is very simple and easy to understand, suitable for digital logic circuit experiment for beginners
Platform: | Size: 415744 | Author: 仲崇鑫 | Hits:

[Other] counter

Description: there is a text file of code for 8 bit up counter in verilog.
Platform: | Size: 1024 | Author: amit | Hits:

[VHDL-FPGA-Verilog] FIFO-and-CAM

Description: verilog code for gray counter,synchronous and asynchronous fifo
Platform: | Size: 25600 | Author: Abhijeet | Hits:

[MiddleWare] Decade-Counter

Description: The file contains source code verilog for counting number of 1s
Platform: | Size: 90112 | Author: dorababugfree | Hits:

[MiddleWare] Johnson-counter-with-verilog-design

Description: the file contains verilog code for johnson counter
Platform: | Size: 43008 | Author: dorababugfree | Hits:

[MiddleWare] Mod13-counter-with-verilog-design

Description: verilog code for mod13 counter source code-verilog code for mod13 counter source code
Platform: | Size: 69632 | Author: dorababugfree | Hits:

[Software Engineering] Counter_AD

Description: Parametrized System Verilog code for a Counter with an increade, decrease switch (AD)
Platform: | Size: 1024 | Author: souhaku | Hits:

[VHDL-FPGA-Verilog] verilog-up-counter

Description: Verilog code for 4 bit Sync Up Counter
Platform: | Size: 11264 | Author: cmags | Hits:

[VHDL-FPGA-Verilog] async_counter_verilog

Description: 这是用verilog 实现的同步计数器。(this is a code for synchronous counter written in verilog.)
Platform: | Size: 6144 | Author: adonis85101 | Hits:
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